Pulse width modulated, or regulated, switched DC/DC power converters are well known in the art. In such power converters, numerous conditions may arise in which the modulating pulse duration undesirably exceeds a predetermined maximum value. Under these conditions, critical circuit components may be overstressed and may consequently fail to operate properly, or may even be degraded or fail. As one example of failure to operate properly, magnetic cores may become saturated by an excessive ON duration of a power switch, which may result in degradation of circuit performance, in turn resulting in poor voltage regulation. Methods for limiting or clamping the pulse width output to prevent overstressing or poor voltage regulation are known.
FIGS. 1a and 1b are representative of two generally similar methods for limiting or clamping the pulse width of a pulse width modulator to prevent component stress. FIG. 1a is a simplified circuit diagram of a DC/DC converter 100 using conventional regulation with clamped maximum duty cycle. In FIG. 1a, a pulse width modulator (PWM) 110 is controlled by the magnitude of an error signal or voltage Ve applied to an input port 110i to produce pulses, illustrated as 105, having controlled duration or width. Such pulse width modulators often include an internal sawtooth- or triangle-signal generator and a comparator, for comparing the sawtooth with the applied error voltage, to generate variable-duration, low-magnitude pulses 105. The low-amplitude pulses 105 produced by PWM 110 of FIG. 1a drive a power amplifier or power switch illustrated as a block 107. As illustrated in block 107, the switch is represented by a mechanical movable switch element 107M which moves in the direction of double-headed arrow 107A under control of the low-level pulses 105, to periodically connect movable element M to a source 103 of unregulated voltage or B+. The resulting high magnitude pulses, illustrated in FIG. 1a as 109, are filtered by a filter, illustrated as 108, to produce direct voltage, and the resulting direct voltage is applied to an output port 145 as the desired output voltage Vo.
In FIG. 1a, the output voltage Vo produced at output port 145 is coupled by way of an attenuator 140, a noninverting amplifier 135, and a comparator 120 input impedance 130 illustrated as a block Zi to the inverting (−) input port 121 of comparator 120. Those skilled in the art know that the input impedance of an input port of a comparator or amplifier is high. A reference voltage Vref is applied by way of a terminal 160 and a filter capacitor 134 to noninverting (+) input port 122 of comparator 120. Those skilled in the art know that a comparator is simply a high-gain amplifier, and may be considered to be such. A feedback impedance Zf 125 is coupled from the output port 120o of comparator 120 to inverting input terminal 121, for interacting with input impedance 130 for controlling the gain of the comparator. Comparator 120 in conjunction with its associated gain controlling resistors 125 and 130 produces an error signal or voltage Ve at its output port 120o for application to input port 110i of PWM 110.
The error signal or voltage Ve produced by comparator 120 of FIG. 1a is a measure of the deviation of the output voltage Vo at terminal 145 from the desired value. The pulse width modulator 110 responds to changes in the value of the error voltage Ve by adjusting the pulse width of pulses 105 in a manner which tends to reduce the difference, all as is well known in the art. The error voltage Ve applied to pulse width modulator 110 may occasionally be of a magnitude which drives PWM 110 to produce a pulse or pulses of undesirably long duration. This might occur, for example, when the PWM is first turned ON, and the voltage at the output of filter 108 does not immediately respond to the pulses from PWM 110.
The arrangement of FIG. 1a includes an error voltage limiting circuit designated generally as 102, connected to conductor 112 at a location electrically between output port 120o of comparator 120 and input port 110i of PWM 110. As illustrated, the voltage limiter 102 includes a zener diode illustrated as 115, having a zener voltage Vz. When the error voltage Ve attempts to rise above the zener voltage of zener diode 115, the zener diode conducts, and tends to limit the voltage rise. Those skilled in the art know that the operation of a limiter of this sort depends, at least in part, upon the impedance of the voltage source, and that it may be necessary or desirable to interpose a further impedance 149 between port 120o and node 150. With zener diode 115 in place, the error voltage which drives the pulse width modulator 110 is limited, and cannot achieve values which call for the undesired pulse widths.
While the arrangement of FIG. 1a is effective, it depends, at least in part, upon the availability of a zener diode which has a zener voltage Vz, or which conducts at an error voltage Ve, corresponding to the threshold between allowable and undesired pulse widths. However, zener diodes are produced only with discrete zener voltages, and a zener diode having the desired zener voltage may not be available. The arrangement of FIG. 1b is similar to that of FIG. 1a, but the voltage limiter 103 substitutes a transistor together with a voltage source for the zener diode of limiter 102 of FIG. 1a. In the arrangement of FIG. 1b, limiter 103 includes a bipolar PNP transistor having its emitter connected to node 150 and its collector grounded. A direct voltage source illustrated by a battery symbol 175 has its negative terminal grounded and its positive terminal connected to the base of transistor 170. The voltage of source 175 may be designated Vm. Transistor 170 will be nonconductive so long as the error voltage Ve at node 150 does not exceed the sum of the voltage Vm of source 175 plus one base-emitter voltage drop (one VBE). When the error signal or voltage Ve at node 150 exceeds Vm+VBE, transistor 170 will conduct to limit the error voltage. The arrangement of FIG. 1b is advantageous by comparison with that of FIG. 1a because the limiting voltage of limiter 103 can be adjusted by simply adjusting the voltage of source 175.
In operation of the arrangements of either FIG. 1a or FIG. 1b, an increase of error voltage Ve tends to increase the pulse width of the pulses produced by PWM 110. At some point during the increase of the error voltage, the limiter 102 or 103 becomes conductive, and prevents any further increase in the error voltage. Consequently, the error voltage can never reach a value such that the undesirably long pulse widths occur.
While these methods are commonly used to clamp the pulse width output, they suffer from long device recovery time when those conditions tending to cause the longer pulse widths are removed. For example, it is known that during a startup, greater pulse widths are produced by pulse width modulator 110 in order to quickly achieve the desired output voltage level. Elaborate schemes, referred to as soft-starts, have been developed to ensure a gradual increase in the operating duty cycle in order to prevent clamping or limiting from occurring. Absent soft-start mechanisms, transient operating conditions associated with the duty cycle may result in clamping at a maximum pulse width that extends over many tens of switching cycles and which unnecessarily overstress components.
FIG. 1c illustrates error voltage Ve and the resulting pulse-width modulated pulses 105 (of FIG. 1a or 1b) during successive time periods of normal operation, during clamping, and during a post-clamping recovery period. In FIG. 1c, an interval of normal operation is designated as 182, which is a subset of times 180. During the interval 182 of normal operation, the error voltage Ve illustrated by plot 112 takes on a range which may be viewed as a normal range. The pulses produced by PWM 110 of FIG. 1a or 1b have a nominal duration in interval 182. Region 185 represents a time during which the error voltage Ve increases toward, and reaches, a limiting voltage. The limiting voltage is variously designated Vz or (VBE+Vm) to represent static (unchanging) zener-diode limiting or transistor limiting, respectively. The resulting pulse durations in region 185 are shown as wide. The condition causing the excessive error voltage Ve is presumed to end at a time lying between time duration 185 and time duration 190. At this time, the error voltage should decrease to the normal region obtaining during the interval 182 of FIG. 1c. However, due to the characteristics of diodes and transistors, there is a recovery time in the interval 190 during which the clamped error voltage remains at the clamp level. Since, in the presence of such a long recovery time, the error voltage cannot decrease to the normal range rapidly during interval 190, at least a portion of the clamped value of error voltage Ve in the interval 190 unnecessarily keeps the pulse width greater than it might otherwise be. After the recovery interval 190, the error voltage lies in the normal range.
Hence, there is a need for a method and apparatus for providing a clamping that provides for more rapid recovery once the event causing duty cycle clamping is removed.